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standard products ut69rh051 radiation-hardened microcontroller data sheet may 2003 features q three 16-bit timer/counters - high speed output - compare/capture - pulse width modulator - watchdog timer capabilities q 256 bytes of on-chip data ram q 32 programmable i/o lines q 7 interrupt sources q programmable serial channel with: - framing error detection - automatic address recognition q ttl and cmos compatible logic levels q 64k external data and program memory space q mcs-51 fully compatible instruction set q flexible clock operation - 1hz to 20mhz with external clock - 2mhz to 20mhz using internal oscillator with external crystal q radiation-hardened process and design; total dose irradia- tion testing mil-std-883 method 1019 - total dose: 1.0e6 rads(si) - latchup immune q packaging options: - 40-pin 100-mil center dip (0.600 x 2.00) - 44-lead 25-mil center flatpack (0.670 x 0.800) q standard microcircuit drawing 5962-95638 available - qml q & v compliant ram port 0 latch port 2 latch port 0 drivers port 2 drivers program address register buffer pc incrementer program counter dptr port 3 latch port 3 drivers port 1 drivers osc. port 1 latch psw tmp3 b register acc stack pointer alu tmp2 tmp1 special function registers, timers, pca, serial port m i c r o - r a m a d d r e s s r e g i s t e r s e q u e n c e r i n s t r u c t i o n r e g i s t e r psen ale ea rst p1.0 - p1.7 p3.0 - p3.7 xtal2 xtal1 figure 1. ut69rh051 microcontroller block diagram
2 1.0 introduction the ut69rh051 is a radiation-tolerant 8-bit microcontroller that is pin equivalent to the mcs-51 industry standard microcontroller when in a 40-pin dip. the ut69rh051?s static design allows operation from 1hz to 20mhz. this data sheet describes hardware and software interfaces to the ut69rh051. 2.0 signal description v dd : +5v supply voltage v ss : circuit ground port 0 (p0.0 - p0.7): port 0 is an 8-bit port. port 0 pins are used as the low-order multiplexed address and data bus during accesses to external program and data memory. port 0 pins use internal pullups when emitting 1?s and are ttl compatible. port 1 (p1.0 - p1.7): port 1 is an 8-bit bidirectional i/o port with internal pullups. the output buffers can drive ttl loads. when the port 1 pins have 1?s written to them, they are pulled high by the internal pullups and can be used as inputs in this state. as inputs, any pins that are externally pulled low sources current because of the pullups. in addition, port 1 pins have the alternate uses shown in table 1. port 2 (p2.0 - p2.7): port 2 is an 8-bit port. port 2 pins are used as the high-order address bus during accesses to external program memory and during accesses to external data memory that uses 16-bit addresses (i.e., movx@dptr). port 2 uses internal pullups when emitting 1?s in this mode. during operations that do not require a 16-bit address, port 2 emits the contents of the p2 special function registers (sfr). the pins have internal pullups and drives ttl loads. port 3 (p3.0 - p3.7): port 3 is an 8-bit bidirectional i/o port with internal pullups. the output buffers can drive ttl loads. when the port 3 pins have 1?s written to them, they are pulled high by the internal pullups and can be used as inputs in this state. as inputs, any pins that are externally pulled low sources current because of the pullups. in addition, port 3 pins have the alternate uses shown in table 2. table 1. port 1 alternate functions table 2. port 3 alternate functions port pin alternate name alternate function p1.0 t2 external clock input to timer/ counter 2 p1.1 t2ex timer/counter 2 capture/reload trigger and direction control p1.2 eci external count input to pca p1.3 cex0 external i/o for pca capture/ compare module 0 p1.4 cex1 external i/o for pca capture/ compare module 1 p1.5 cex2 external i/o for pca capture/ compare module 2 p1.6 cex3 external i/o for pca capture/ compare module 3 p1.7 cex4 external i/o for pca capture/ compare module 4 port pin alternate name alternate function p3.0 rxd serial port input p3.1 txd serial port output p3.2 int0 external interrupt 0 p3.3 int1 external interrupt 1 p3.4 t0 external clock input for timer 0 p3.5 t1 external clock input for timer 1 p3.6 wr external data memory write strobe p3.7 rd external data memory read strobe
3 rst: reset input. a high on this input for 24 oscillator periods while the oscillator is running resets the device. all ports and sfrs reset to their default conditions. internal data memory is undefined after reset. program execution begins within 12 oscillator periods (one machine cycle) after the rst signal is brought low. rst contains an internal pulldown resistor to allow implementing power-up reset with only an external capacitor. ale: address latch enable. the ale output is a pulse for latching the low byte of the address during accesses to external memory. in normal operation, the ale pulse is output every sixth oscillator cycle and may be used for external timing or clocking. however, during each access to external data memory (movx instruction), one ale pulse is skipped. psen : program store enable. this active low signal is the read strobe to the external program memory. psen activates every sixth oscillator cycle except that two psen activations are skipped during external data memory accesses. ea : external access enable. this pin should be strapped to v ss (ground) for the ut69rh051. xtal1: input to the inverting oscillator amplifier. xtal2: output from the inverting oscillator amplifier. 2.1 hardware/software interface 2.1.1 memory the ut69rh051 has a separate address space for program and data memory. internally, the ut69rh051 contains 256 bytes of data memory. it addresses up to 64kbytes of external data memory and 64kbytes of external program memory. 2.1.1.1 program memory there is no internal program memory in the ut69rh051. all program memory is accessed as external through ports p0 and p2. the ea pin must be tied to v ss (ground) to enable access to external locations 0000 h through 7fff h . following reset, the ut69rh051 fetches the first instruction at address 0000h. 2.1.1.2 data memory the ut69rh051 implements 256 bytes of internal data ram. the upper 128 bytes of this ram occupy a parallel address space to the sfrs. the cpu determines if the internal access to an address above 7f h is to the upper 128 bytes of ram or to the sfr space by the addressing mode of the instruction. if direct addressing is used, the access is to the sfr space. if indirect addressing is used, the access is to the internal ram. stack operations are indirectly addressed so the upper portion of ram can be used as stack space. figure 3 shows the organization of the internal data memory. the first 32 bytes are reserved for four register banks of eight bytes each. the processor uses one of the four banks as its working registers depending on the rs1 and rs0 bits in the psw sfr. at reset, bank 0 is selected. if four register banks are not required, use the unused banks as general purpose scratch pad memory. the next 16 bytes (128 bits) are individually bit addressable. the remaining bytes are byte addressable and can be used as general purpose scratch pad memory. for addresses 0 - 7f h , use either direct or indirect addressing. for addresses larger than 7f h , use only indirect addressing. in addition to the internal data memory, the processor can access 64kbytes of external data memory. the movx instruction accesses external data memory. 2.1.2 special function registers table 3 contains the sfr memory map. unoccupied addresses are not implemented on the device. read accesses to these addresses will return unknown values and write accesses will have no effect.
4 (t2) p1.0 (t2ex) p1.1 (eci) p1.2 (cex0) p1.3 (cex1) p1.4 (cex2) p1.5 (cex3) p1.6 (cex4) p1.7 rst (rxd) p3.0 (txd) p3.1 ( int0 ) p3.2 ( int1 ) p3.3 (t0) p3.4 (t1) p3.5 ( wr ) p3.6 ( rd ) p3.7 xtal2 xtal1 v ss v dd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea ale psen p2.7 (a15) p2.6 (a14) p2.5 (a13) p2.4 (a12) p2.3 (a11) p2.2 (a10) p2.1 (a9) p2.0 (a8) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 23 24 22 21 v ss (t2) p1.0 (t2ex) p1.1 nc (eci) p1.2 (cex0) p1.3 (cex1) p1.4 (cex2) p1.5 (cex3) p1.6 (cex4) p1.7 rst (rxd) p3.0 (txd) p3.1 ( into ) p3.2 ( int1 ) p3.3 ( to) p3.4 (t1) p3.5 ( wr ) p3.6 ( rd ) p3.7 xtal2 p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) ea ale psen p2.7 (a15) p2.6 (a14) p2.5 (a13) p2.4 (a12) p2.3 (a11) p2.2 (a10) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 17 19 20 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 27 28 26 25 21 22 24 23 xtal1 v ss v dd p2.1 (a9) p2.0 (a8) nc v dd figure 2a. ut69rh051 40-pin dip connections figure 2b. ut69rh051 44-pin flatpack connections
5 figure 3. internal data memory organization 2.1.3 reset the reset input is the rst pin. to reset, hold the rst pin high for a minimum of 24 oscillator periods while the oscillator is running. the cpu generates an internal reset from the external signal. the port pins are driven to the reset state as soon as a valid high is detected on the rst pin. while rst is high, psen and the port pins are pulled high; ale is pulled low. all sfrs are reset to their reset values as shown in table 3. the internal data memory content is indeterminate. the processor will begin operation one machine cycle after the rst line is brought low. a memory access occurs immediately after the rst line is brought low, but the data is not brought into the processor. the memory access repeats on the next machine cycle and actual processing begins at that time. f8 f0 88 80 78 70 38 30 28 20 18 10 08 00 ff f7 8f 87 7f 77 3f 37 2f 27 1f 17 0f 07 indirect access only direct or indirect access scratch pad area bit addressable segment register banks 8 bytes
6 notes: 1. values shown are the reset values of the registers. 2. x = undefined. table 3. sfr memory registers f8 ch 00000000 ccap0h xxxxxxxx ccap1h xxxxxxxx ccap2h xxxxxxxx ccap3h xxxxxxxx ccap4h xxxxxxxx ff f0 b 00000000 f7 e8 cl 00000000 ccap0l xxxxxxxx ccap1l xxxxxxxx ccap2l xxxxxxxx ccap3l xxxxxxxx ccap4l xxxxxxxx ef e0 acc 00000000 e7 d8 ccon 00x00000 cmod ooxxx000 ccapm0 x00000000 ccapm1 x00000000 ccapm2 x00000000 ccapm3 x00000000 ccapm4 x00000000 df d0 psw 00000000 d7 c8 t2con 00000000 t2mod xxxxxx00 rcap2l 00000000 rcap2h 00000000 tl2 00000000 th2 00000000 cf c0 c7 b8 ip x0000000 saden 00000000 bf b0 p3 11111111 iph x00000000 b7 a8 ie 00000000 saddr 00000000 af a0 p2 11111111 a7 98 scon 00000000 sbuf xxxxxxxx 9f 90 p1 11111111 97 88 tcon 00000000 tmod 00000000 tl0 00000000 tl1 00000000 th0 00000000 th1 00000000 8f 80 p0 11111111 sp 00000111 dpl 00000000 dph 00000000 pcon 00xx00xx 87
7 3.0 radiation hardness the ut69rh051 incorporates special design and layout features which allow operation in high-level radiation environments. utmc has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both the gate oxide and the field oxide while maintaining the circuit density and reliability. for transient radiation hardness and latchup immunity, utmc builds all radiation-hardened products on epitaxial wafers using an advanced twin-tub cmos process. in addition, utmc pays special attention to power and ground distribution during the design phase, minimizing dose- rate upset caused by rail collapse. radiation hardness design specifications 1 note: 1. worst case temperature t a = +125 c. 2. adams 90% worst case environment (geosynchronous). 4.0 absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. e xposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. test per mil-std-883, method 1012. total dose 1.0e6 rad(si) let threshold 20 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 saturated cross-section (1kx8) 1e-4 cm 2 /device single event upset 1.3e-7 errors/device-day 2 single event latchup 1 let>128 mev-cm 2 /mg symbol parameter limits units v dd dc supply voltage -0.5 to 7.0 v v i/o voltage on any pin -0.5 to v dd +0.3v v t stg storage temperature -65 to +150 c p d maximum power dissipation 750 mw t j maximum junction temperature 175 c q jc thermal resistance, junction-to-case 2 10 c/w i i dc input current 10 ma
8 5.0 dc electrical characteristics (pre/post-radiation)* v dd = 5.0v 10%; ta = -55 c < t c < +125 c) notes: * post-radiation performance guaranteed at 25 c per mil-std-883. 1. under steady state (non-transient) conditions, i ol must be limited externally as follows: maximum i ol per port pin: 10ma maximum i ol per 8-bit port- port 0: 26ma ports 1, 2, & 3: 15ma maximum total i ol for all output pins: 71ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 2. capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the v ol of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1 to 0 transitions during bus operations. in appli cations where capacitance loading exceeds 100 pf, the noise pulse on the ale may exceed 0.8v. in these cases, it may be desirable to qualify ale with a schmitt t rigger or use an address latch with a schmitt trigger strobe input. 3. capacitive loading ports 0 and 2 cause the v oh on ale and psen to drop below the vdd-0.3 specification when the address lines are stabilizing. 4. capacitance measured for initial qualification or design changes which may affect the value. symbol parameter condition minimum maximum unit v il low-level input voltage 0.8 v v ih high-level input voltage (except xtal, rst) 2.0 v v ih1 high-level input voltage (xtal) 3.85 v v ol low-level output voltage 1 (ports 1, 2 and 3) i ol = 100 m a 0.3 v i ol = 1.6ma 0.45 v i ol = 3.5ma 1.0 v v ol1 low-level output voltage 1,2 (port 0, ale, psen , prog ) i ol = 200 m a 0.3 v i ol = 3.2ma 0.45 v i ol = 7.0ma 1.0 v v oh high-level output voltage 3 (ports 1, 2, and 3 ale and psen ) i oh = -10 m a 4.2 v i oh = -30 m a 3.8 v i oh = -60 m a 3.0 v v oh1 high-level output voltage (port 0 in external bus mode) i oh = -200 m a 4.2 v i oh = -3.2ma 3.8 v i oh = -7.0ma 3.0 v i il logical 0 input current (ports 1, 2, and 3) v in = 0.0v v cc = 5.5v -50 -65 m a i il logical 0 input current (xtal 1) v in = 0.0v v cc = 5.5v -65 m a i li input leakage current (port 0) v in = 0.0v or v cc v cc = 5.5v 25 65 m a i li input leakage current (xtal1) v in = 0.0v or v cc v cc = 5.5v 65 m a c io 4 pin capacitance @ 1mhz, 25 c 15 pf i dd power supply current: @16mhz @20 mhz 95 120 ma
9 figure 4. i dd test condition, active mode all other pins disconnected figure 5. clock signal waveform for i dd tests in active and idle modes t clch = t chcl = 5ns v dd v dd i dd v dd v dd rst p0 ea v ss xtal2 xtal1 clock signal (nc) t clch = t chcl = 5ns gnd v dd -0.5 0.45v 0.2 v dd -0.1 0.7 v dd t clcl t chcl t chcx t chcx t clch
10 6.0 ac characteristics read cycle (post-radiation)* (v dd = 5.0v 10%; -55 c < t c < +125 c) note: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019 at 1.0e6 rads(si). 1. guaranteed, but not tested. symbol parameter minimum maximum unit t clcl clock period 50 ns 1/t clcl oscillator frequency 20 mhz t lhll ale pulse width 2 t clcl -40 ns t avll address valid to ale low t clcl -40 ns t llax 1 address hold after ale low t clcl -30 ns t lliv ale low to valid instruction 4 t clcl -100 ns t llpl ale low to psen low t clcl -30 ns t plph psen pulse width 3 t clcl -45 ns t pliv psen low to valid instruction in 3 t clcl -105 ns t pxix 1 input instruction hold after psen 0 ns t pxiz 1 input instruction float after psen t clcl -25 ns t aviv address to valid instruction in 5 t clcl -105 ns t plaz 1 psen low to address float 10 ns t rlrh rd pulse width 6 t clcl -100 ns t wlwh wr pulse width 6 t clcl -100 ns t rldv rd low to valid data in 5 t clcl -165 ns t rhdx 1 data hold after rd high 0 ns t rhdz 1 data float after rd high 2 t clcl -60 ns t lldv ale low valid data in 8 t clcl -150 ns t avdv address to valid data in 9 t clcl -165 ns t llwl ale low to rd or wr low 3 t clcl -50 3 t clcl +50 ns t avwl address valid to wr low 4 t clcl -130 ns t qvwx data valid before wr high t clcl -33 ns t whqx data hold after wr high t clcl -33 ns t qvwh data valid to wr high 7 t clcl -150 ns t rlaz 1 rd low to address float 0 ns t whlh rd or wr high to ale high t clcl -40 t clcl +40 ns
11 figure 6. external program memory read timing waveforms figure 7. external data memory read cycle waveforms figure 8. external data memory write cycle waveforms ale t plph psen t lhll t avll t llpl t lliv port 0 port 2 t aviv a8 - a15 a8 - a15 a0 - a7 a0 - a7 instr in t llax t plaz t pxiz t pxix t pliv ale t lhll port 0 port 2 t avdv p2.0 - p2.7 or a8 -a15 from dph a8 - a15 from pch a0 -a7 from ri or dpl instr in psen rd data in a0 - a7 from pcl t avwl t llax t whlh t lldv t llwl t rlrh t avll t rlaz t rldv t rhdz t rhdx ale t lhll port 0 port 2 p2.0 - p2.7 or a8 -a15 from dph a8 - a15 from pch a0 -a7 from ri or dpl instr in psen wr data out a0 - a7 from pcl t avwl t llax t whlh t llwl t wlwh t avll t whqx t qvwx t qvwh
12 7.0 serial port timing characteristics (v dd = 5.0v 10%; -55 c < t c < +125 c) note: 1. guaranteed, but not tested. figure 9. serial port timing waveforms 8.0 external clock drive timing characteristics note: 1. guaranteed, but not tested. figure 10. external clock drive timing waveforms symbol parameter minimum maximum unit t xlxl 1 serial port clock period 12 t clcl -10 12 t clcl +10 ns t qvxh output data setup to clock rising edge 10 t clcl -133 ns t xhqx output data hold after clock rising edge 2 t clcl -70 ns t xhdx 1 input data hold after clock rising edge 0 ns t xhdv clock rising edge to input data valid 10 t clcl -133 ns symbol parameter minimum maximum unit 1/t clcl oscillator frequency 20 mhz t chcx high time 16 ns t clcx low time 16 ns t clch rise time 20 ns t chcl fall time 20 ns ale output data (write to sbuf) clock 0 1 2 3 4 5 6 7 8 t xlxl t xhqx t qvxh t xhdx 0 1 2 3 4 5 6 7 t xhdv set ti set ri input data (clear ri) valid valid valid valid valid valid valid valid t chcx t clcl t clch t chcx v dd - 0.5 0.45 v 0.7 v dd 0.2 v dd - 0.1 t chcl
13 9.0 packaging notes: 1. all package finishes are per mil-prf-38535. 2. letter designations are for cross-reference mil-std-1835. e 0.595 + 0.010 end view side view l 0.200 0.125 b 0.018 + 0.002 0.100 e s2 0.005 min. typ. d 2.000 + 0.025 a 0.185 max. top view pin 1 i.d. (geometry optional) c 0.010 + 0.002 - 0.001 s1 0.005 min. typ. 0.600 figure 11. 40-pin side-brazed dip
14 c notes: 1. all exposed metalized areas to be plated per mil-prf-38535. 2. dimension letters refer to mil-std-1835. figure 12. 44-lead flatpack
15 appendix a difference between industry standard and ut69rh051 the areas in which the ut69rh051 differs from the industry standard will be covered in this section. in this discussion, industry standard will be used generically to refer to all speed grades including the 20mhz. 1.0 reset the ut69rh051 requires the rst input to be held high for at least 24 oscillator periods to guarantee the reset is completed in the chip. also, the port pins are reset asynchronously as soon as the rst pin is pulled high. on the ut69rh051 all portions of the chip are reset synchronously when the rst pin is high during a rising edge of the input clock. when coming out of reset, the industry standard takes 1 to 2 machine cycles to begin driving ale and psen immediately after the rst is removed, but the access during the first machine cycle after reset is ignored by the processor. the second cycle will repeat the access and processing will begin. 2.0 power saving modes of operation 2.1 idle mode idle mode and the corresponding control bit in the pcon sfr have not been implemented in the ut69rh051. setting the idle control bit has no effect. 2.2 power down mode power down mode and the corresponding control bit in the pcon register have not been implemented in the ut69rh051. setting the power down control bit has no effect. also, the power off flag in the pcon has not been implemented. 3.0 on circuit emulation the on circuit emulation mode of operation in the industry standard has not been implemented in the ut69rh051. 4.0 operating conditions the operating voltage range for the industry standard is 5v + 20%. the operating temperature range is 0 c to 70 c. on the ut69rh051, the operating voltage range is 5v + 10%. the operating temperature range is -55 c to +125 c.
16 appendix b impact of external program rom the 8051 family of microcontrollers, including the industry standards, use ports 0 and 2 to access external memory. in implementations with external program memory, these two ports are dedicated to the program rom interface and can not be used as input/output ports. the ut69rh051 uses external program rom, so ports 0 and 2 will not be available for i/o.
17 ordering information ut69rh051 microcontroller: smd lead finish: (a) = solder (c) = gold (x) = optional case outline: (q) = 40-pin dip (y) = 44-pin flatpack class designator: (q) = class q (v) = class v device type (01) = 8-bit microcontroller drawing number: 95638 total dose: (h) = 1e6 rads(si) (g) = 5e5 rads(si) (f) = 3e5 rads(si) (r) = 1e5 rads(si) federal stock class designator: no options 5962 * 95638 * * * * notes: 1. lead finish (a, c, or x) must be specified. 2. if an ?x? is specified when ordering, part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.
18 ut69rh051 microcontroller ut **** * ** - * * * * total dose: ( ) = none lead finish: (a) = solder (c) = gold (x) = optional screening: (c) = mil temp (p) = prototype package type: (p) = 40-pin dip (w) = 44-pin flatpack device type: (ut69rh051) = 8-bit microcontroller notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (g old). 3. radiation characteristics are neither tested nor guaranteed and may not be specified. 4. devices have prototype assembly and are tested at 25 c only. radiation characteristics are neither tested nor guaranteed and may not be specified.

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